1. Field of the Invention
The present invention relates to a phase calibration device and a phase calibration method, especially to a phase calibration device and a phase calibration method applicable to a data recovery system.
2. Description of Related Art
Regarding the Ethernet network communication system, there is a clock generation circuit in each of the transmission end and the reception end. The two clock generation circuits work separately, which means that their generated clocks are not in a direct correlation. However, the reception end needs to recover the data delivered by the transmission end correctly, and thus the clock generation circuit in the reception end should generate a clock which is similar to or somehow related to the clock of the transmission end. But since the clock generation basis of the reception end (e.g. a crystal oscillator) is different from the clock generation basis of the transmission end (e.g. another crystal oscillator), the clock frequencies thereof are unavoidably different from each other. Therefore, the reception end needs to perform clock adjustment every few moments to thereby retrieve an optimal sampling position for sampling data correctly. According to the current art, the reception end uses its clock generation circuit to generate several clocks having the same frequency but different phases, picks an optimal sampling clock among the clocks by analyzing the sampled data, and then samples the following data according to the optimal sampling clock. As described before, the reception end needs to do clock adjustment every few moments for compensating the frequency difference between it and the transmission end; therefore, when the reception end detects deterioration in the sampled data, it will select another clock having a different phase among the aforementioned several clocks to use it as the updated optimal sampling clock for sampling the following data, so as to make sure that the sampled data remain acceptable.
However, in order to save power consumption, some Ethernet network reception end will shut down partial components (e.g. the phase lock loop in the clock generation circuit) in the leisure time to save power. But the reception end also has to return to normal work immediately when data are coming in, which means that the reception end has to quickly choose the optimal sampling clock again for sampling data. Because the phase lock loop, for example, which was shut down and restarted through the power saving process, might output an incorrect clock or couldn't continue the earlier work smoothly, sampling error consequence could therefore happen to the back-end circuits. As a result, the reception end must find the optimal sampling clock among the aforementioned several clocks according to the sampled data again. This repeated process not only consumes time but also lowers the power saving effect.